As conventional semiconductor devices, insulated gate semiconductor devices disclosed in patent references 1 and 2 are known. In these insulated gate semiconductor devices, by applying a gate voltage to an insulated gate, a field effect is produced in a channel region in a semiconductor substrate, and current flows between emitter and collector. Accordingly, a contact opening is provided in order to exchange carriers between an emitter region and an emitter electrode. A typical example of this kind of insulated gate semiconductor device has a structure as shown in FIG. 18 to FIG. 20. FIG. 18 and FIG. 20 are longitudinal sectional views, and FIG. 19 is a plan sectional view of level A-A in these drawings. FIG. 18 is a sectional view of position B-B in FIG. 19 and FIG. 20. FIG. 20 is a sectional view of position C-C in FIG. 18 and FIG. 19.
In the insulated gate semiconductor device shown in FIG. 18 to FIG. 20, on the principal plane of level A-A side of semiconductor substrate, N+ emitter region 904 and P+ emitter region 900 are provided. Contacting with the lower part of them, P body region 903 is disposed. Further beneath the P body region 903, N drift region 902 is provided, and P+ collector region 901 is provided furthermore beneath. So far is within a semiconductor substrate (in this specification, the entire semiconductor single crystal of a start wafer and a layer formed by epitaxial growth on its surface is called a semiconductor substrate). In the semiconductor substrate, still more, P field regions 911 for dividing individual devices are formed from the level A-A side. Bottoms of the P field regions 911 reach into the N drift region 902.
Part of the semiconductor substrate is dug in from the level A-A side, and gate electrodes 906 are provided in the cavity. Gate electrodes 906 are insulated from the regions within the semiconductor substrate by gate insulating films 905. Above the semiconductor substrate, emitter electrode 909 and gate wirings 916 are provided. The emitter electrode 909 is an electrode conducting to N+ emitter region 904 and P+ emitter region 900 within a range of contact opening 908. The gate wiring 916 conducts with gate electrodes 906 in other position than shown. Gate electrodes 906 and gate wiring 916 are insulated from other parts by interlayer insulating film 907. Beneath the semiconductor substrate, collector electrode 910 is provided.
In this structure, when a power voltage is applied between the emitter electrode 909 and collector electrode 910, by on/off switching of gate voltage to gate electrodes 906, current between the emitter electrode 909 and the collector electrode 910 can be switched. Herein, contact opening 908 which is a contact region between the emitter region (N+ emitter region 904 and P+ emitter region 900) and emitter electrode 909 is formed in a rectangular shape in FIG. 19. This is intended to increase the area of the contact opening 908 and heighten the latch-up resistance while avoiding short-circuiting to gate electrodes 906 and gate wirings 916.
Patent reference 1, Japanese Patent Publication No. H6-101565
Patent reference 2, Japanese Laid-open Patent No. H10-229191
Such conventional semiconductor device, however, had a problem of local heating after switching off. The cause lies in the shape of the contact opening 908. That is, after switching off, as indicated by arrow I in FIG. 21, hole current from P field region 911 flows into the emitter electrode 909. As shown in FIG. 22, this hole current density is high at four corners of the rectangular contact opening 908. There is no contact opening 908 in a region between devices, and holes in the P field region 911 are directed toward the nearest contact opening 908. As a result, when interrupting a large current, in particular, the device may be destructed due to excessive heat generation. This phenomenon is prominent at corners of terminal end of device array.
As means for lessening concentration of current, simply, it may be considered to increase the area of contact opening 908. But it is limited in relation to insulation from gate electrodes 906 and others. If the contact opening 908 is excessively increased in area, holes may pass through the emitter electrode 909 too much in ON state. As a result, ON voltage becomes higher. It is hence difficult to increase the area of the contact opening 908.
The present invention is devised to solve these problems of the conventional semiconductor device. It is hence an object thereof to present a semiconductor device capable of stable operation of large current by lessening current concentration at corners of contact opening after switching off and suppressing local heat generation, without heightening ON voltage.